1. Field of the Invention
The present invention relates to a clock circuit, and more particularly, to a clock circuit with delay functions and a related delay method.
2. Description of the Prior Art
Clock balancing technology can be divided into the “inter-clock balancing” technology and the “intra-clock balancing” technology. Herein the inter-clock balancing technology aims at maintaining the same latency between two different clock trees in order to satisfy the requirements of setup times. While the intra-clock balancing technology aims at maintaining the same total delay time between different sub-trees among the same clock tree in order to balance this clock tree.
Recently a common approach is that adding delay units (e.g., buffers) one by one into the clock tree (or the sub-tree) having a shorter delay time, such that the clock tree (or the sub-tree) having the shorter delay time can be balanced. However, such an approach needs a larger number of delay units (e.g., buffers), which is not ideal for considerations to cost and layout. Moreover, each of the delay unit (e.g., buffer) has a minimum delay time, which results in a low delay resolution.